SPARC
| Designer | Sun Microsystems (acquired by Oracle Corporation)[1][2] |
|---|---|
| Bits | 64-bit (32 → 64) |
| Introduced | 1986 (production) 1987 (shipments) |
| Version | V9 (1993) / OSA2017 |
| Design | RISC |
| Type | Load–store |
| Encoding | Fixed |
| Branching | Condition code |
| Endianness | Bi (Big → Bi) |
| Page size | 8 KB (4 KB → 8 KB) |
| Extensions | VIS 1.0, 2.0, 3.0, 4.0 |
| Open | Yes, and royalty free |
| Registers | |
| General-purpose | 31 (G0 = 0; non-global registers use register windows) |
| Floating-point | 32 (usable as 32 single-precision, 32 double-precision, or 16 quad-precision) |
SPARC (Scalable Processor ARChitecture) is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems. Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s. First developed in 1986 and released in 1987, SPARC was one of the most successful early commercial RISC systems, and its success led to the introduction of similar RISC designs from many vendors through the 1980s and 1990s. After acquiring Sun, Oracle Corporation ended SPARC development in 2017, although development of SPARC processors by Fujitsu continues.